Flow block

Flow block is part of Hybrid Design Flow (HDF). the block is control flow directive to tell the Kathryn how to manage the control flow of the hardware via Node.

Flow Block Structure

src/model/flowBlock/abstract/flowBlock_Base.h

FlowIdentfiable assist flow block to have a name, id, flow localization.
ModelDebuggable is and interface for debugger.
simplified FlowBlockBase FlowBlockBase

 
class FlowBlockBase{
 
    std::vector<FlowBlockBase*> _subBlocks;
    std::vector<int>            _subBlocksOrder;
    std::vector<FlowBlockBase*> _conBlocks;
    std::vector<int>            _conBlocksOrder;
    std::vector<Node*>          _basicNodes;
    std::vector<int>            _basicNodesOrder;
    std::vector<Node*>          _sysNodes;
 
    OprNode*                      intNodes  [INT_CNT];
 
    virtual NodeWrap*   sumarizeBlock() = 0;
    virtual void        buildHwComponent() = 0;
 
}

_subBlocks is the collection of block, belonging to current block.
_conBlocks is the collection of block, chaining with current block such as elif block is the conblock of cif block.
_basicNodes and _sysNodes is the collection of node, belonging to current block.
intNodes is the collection of interrupt node.
*Order is the vectors that contain order of its related components by sequence of user declaration
sumarizeBlock() is used to build Flow Block representation NodeWrap which contain entrance and exit nodes.
buildHwComponent() is used to build hardware component coresponding to its nodes and blocks.

Flow Block Types

This session introduces provided Flow Block in Kathryn and illustrates how node is composed coresponding to Flow Block type.

Sequential Block

src/model/flowBlock/seq/seq.h
this block will arrange the its node, subBlock, and conBlock Sequentially coresponding to designers' input

seq{
  a = 48;             ///// take 1 cycle
  cwhile(x < a)      ///// cwhile block take N/A cycle
      x <<= x + 3;    ///// x and y assignment will run sequentially too
      y <<= y + 3;    /////
  b = 24;             ///// take 1 cycle
}                    ///// total cycle usage = 2 + cwhile's cycle usage

the node diagram will be like this

Parallel Block

src/model/flowBlock/par/par.h
this block will arrange the its node, subBlock, and conBlock Parallelly coresponding to designers' input
in case, kathryn cannot determine cycle usage of its subBlock

par{
  a = 48;             ///// take 1 cycle
  cwhile(x < a){      ///// cwhile block take N/A cycle 
      x <<= x + 3;    ///// x and y assignment will run parallely
      y <<= y + 3;    /////
  }
  b = 24;             ///// take 1 cycle
}

the node diagram will be like this

in case, kathryn can determine all cycle usage of its subBlock

par{
  a = 48;             ///// take 1 cycle
  cwhile(x < a)
      seq{      ///// seq take 2 cycle
          x <<= x + 3;    ///// x and y assignment will run for 2 cycle
          y <<= y + 3;    /////
      }
  b = 24;             ///// take 1 cycle
}

the node diagram will be like this

$n_{ssync}$ selects only node wrap as a trigger not $n_sm1$ because it can be sure that $n_{sm1}$ has finished execute already.
Additionally, if there is any SINGLE subBlock marked with markAsMasterJoin, the $n_{msync}$ node will only listen the exit signal from the marked block (cwhile(z < b) block in this case). The marker also serves as resource usage optimization because when designers deeply know the behavior of the hardware flow and mark the block, kathryn won't generate unnecessary synchronization hardware logic.

par{
  a = 48;             ///// take 1 cycle
  cwhile(x < a){      ///// seq take 2 cycle
      x <<= x + 3;    ///// x and y assignment will run sequentially too
      y <<= y + 3;    /////
  }
  cwhile(z < b){ markAsMasterJoin
      z <<= z + 2;
  }
  b = 24;             ///// take 1 cycle
}

the node diagram will be like this

Conditional Block

src/model/flowBlock/cond
this block will arrange node according to condition that designers specify

C/S condition

the task inside conditional block (cif, celif, celse, sif, selif, selse) will be arrange coresponding to the flow mechanism (sequentially/ parrallelly) of the nearest outter block that it can be determined.
if there is no detectable outter block, it will automatically set to parrallel.

[c/s]if(x){
  a = 48;
  b = 24;
}[c/s]elif(y){
  c = 50;
  d = 25;
}

the node diagram will be like this

Z condition

the task inside the Z block can be only cycle-consider element (assignment <<= or =)
it will be group to a signle state node

zif(x){
  a = 48;
  b = 24;
}zelif(y){
  c = 50;
  d = 25;
}

the node diagram will be like this

Loop Block

src/model/flowBlock/loop
this block will arrange node according to condition and loop type that designers specify

C/S/CDO condition

the task inside loop block (cwhile, swhile, cdowhile) will be arrange coresponding to the flow mechanism (sequentially/ parrallelly) of the nearest outter block that it can be determined.
if there is no detectable outter block, it will automatically set to parrallel.

[c/s/cdo]while(x){
  a = 48;
  b = 24;
}

the node diagram will be like this

Pipeline Block

src/model/flowBlock/pipeline

It composes of two major component:

pipWrap is the flow directive to command the order of pipBlk
pipBlk is the loop block which synchronizes with its consecutive block
the task inside pipBlk will be treated as Sequential task.

  pipWrap{
      pipBlk{
          a <<= a + 1;
      }
      pipBlk{
          b <<= a + 1;
      }
      pipBlk{
          cif(b == 10){
              syWait(100)
          }celse{
              c <<= b + 1;
          }
      }
      pipBlk{
          d <<= c + 1;
      }
  }

Timming Block

src/model/flowBlock/time/wait.h
It is used to delay the hardware flow
```
  scWait(x)
  syWait(100);
```

Node Controller