Hybrid Design Flow (HDF) Introduction

To describe the hardware behavior, The Hybrid Design Flow (HDF) is the design method that is used to describe the behavior of the hardwire design.

• hybrid state-machine can be the same behavior as finite state-machine that many users used to describe in Verilog or other Hardware Description languages or the behavior that I offer in these sub sections

• User can describe the HDF by writting it in the void flow() function or any place/method that void flow() can call

• Kathryn will call the flow function after User start using startModelKathryn()

• main.cpp

  #include "kathryn.h"
  using namespace kathryn;
   
  class ExModule: public Module{
  public:
   
      ExModule(int x): Module(){}
   
      void flow() override{
            // v---------- put your design flow here
            //             or other place that flow call
      }
  };