Generating

Kathryn provides hardware generating by transpile the declared model into Verilog.

Internally, the generator take 4 following stage to generate the Verilog file.
- 1. initEle: it collect all meta-data of Module and LogicElement to seperated storage.
- 1. routeIo: Because Kathryn supports high flexible LogicElement wiring, This stage is to route for neccessary traditional module generation.
- 1. compared: This section is used to reduce redundant Verilog generation by compare each module to previous built module and discard redundant generation.
- 1. generate: This section will generate Verilog file from the refined model (all previous section).

Example generating code

#include "kathryn.h"
using namespace kathryn;
 
class ExampleModule: public Module{        
        /////  your code
};
 
int main(int argc, char* argv[]){ //// first input operand must be the parameter file path
    auto params = readParamKathryn(argv[1]);
    mMod(ex, ExampleModule, 0);
    startModelKathryn();
    startGenKathryn(params);
    resetKathryn();
}

auto params = readParamKathryn(argv[1]); is used to read parameter from file
mMod(ex, ExampleModule, 0); is used to make module.
startModelKathryn(); is usesd to compose the hardware model the flow will now be used here.
startGenKathryn(params); is used to generate Verilog file
resetKathryn() is used to reset system and prepare for next operation (new model!)

Example parameter file

; gen Path is prefix
genPath = /media/tanawin/tanawin1701e/project2/Kathryn/KOut/genExample/tutorial.v

5.Dump Vcd File Example Projects