RISC-V Out-of-Order CPU (Kride)

• We introduce the RISC-V Out-of-Order CPU to demonstrate the capabalities of Kathryn in complex architecture modeling
• We implemented it based on RIDE CPU, discarding G-share predictor RIDE CORE (opens in a new tab)
• Our model is at KRIDE CORE (opens in a new tab)

Pipeline Specification

The CPU is composed of 6 pipeline stages as following blocks:

1. Fetch Stage: This stage uses the program counter as an instruction memory indexer; it will recruit 4 32-bit consecutive instructions from the integrated memory; however, at most two instructions are allowed to be placed into the “Fetch Stage Latch”.

2. Decode Stage: The fetched instructions from the previous stage are decoded into microarchitectural data and metadata. In addition, the Speculative tag generator also allocates the new tag in this stage if the decoded instruction is a branch instruction.

3. Dispatch Stage: This stage translates the architecture register to a physical register to avoid data dependency hazard. In other words, the Architecture Register File (ARF) and Renamed Register File (RRF) entries are initialized and modified in this stage; Moreover, not only will the matched reservation station be allocated and filled in this stage, but also the reorder buffer will be allocated as well. Actually, this is the most complicated stage because it has to communicate with several parts of the hardware.

4. Select & Wakeup: This stage will wake up the ready micro-operation in the reservation station and push it into the execution stage. Additionally, the ready condition is determined by the availability of all source data for execution; nevertheless, the instruction’s speculative status is not counted into the ready condition.

5. Execution: This stage will execute the data provided from the previous stage. The result then bypasses the dispatch and reservation stages, writes a 1 to the RRF, and notifies the reorder buffer.

6. Reorder Buffer (ROB): This stage will sequentially update the finished instruction and update the renaming information and its data to ARF and RRF.

Pipeline Conditions

timing management is extremely complex due to control and data dependency. In this section, we present the clarified handling event for each event for each pipeline stage in this current CPU design.

Pipeline Block

Tag Management

Register Architecture