Dev Book
Simulation
genFile

Generated model file

  • This session will describe the context that Kathryn generate the hardware simulation model file

  • This code below is the simplified version of generated file

     
    void ProxySimEvent::startVcdDecVarInternal(){}
    void ProxySimEvent::startVcdDecVarUser(){}
    void ProxySimEvent::startRegisterCallBack(){}
 
    __attribute__((always_inline)) inline bool checkCallBack(){}
 
 
      __attribute__((always_inline)) inline void startMainOpEleSimSke(){}
      __attribute__((always_inline)) inline void startVcdColInternalSke(){}
      __attribute__((always_inline)) inline void startVcdColInternalSke(){}
      __attribute__((always_inline)) inline void startFinalizeEleSimSke(){}
      __attribute__((always_inline)) inline void startPerfColSke(){}
      CYCLE mainSimSke(CYCLE kathryn_longrangeLim){}
      CYCLE ProxySimEvent::mainSim(){}
      extern "C" ProxySimEventBase* create(){}

  • The main simulation from the main program can make decision to simulate this model more than one cycle at a time, because of performance optimization; therefore, Kathryn provides callBackMethod to make the model automatically kick back from generated simulation to main simulation.

  • The default generate is in modelCompile/generated folder

Ske methods

  • Ske means skeleton. It is supposed to be the essential function to do the simulation and It must be run as fast as possible.

    • startMainOpEleSimSke(){} does the main simulation of all logic element but not update the value for register and memory block.
    • startVcdColInternalSke(){} collects all internal signal data and put to vcd file.
    • startVcdColUserSke(){} collects all user signal data and put to vcd file.
    • startFinalizeEleSimSke(){} update the value for register and memory block.
    • startPerfColSke(){} colects the performance for zep

  • vcd and Perf col may be not generated if the simulation parameter at src/simParam.cpp is set to not simulate that things.

general methods

  • startVcdDecVarInternal() declares the internal signal variable to VCD file writer.
  • startVcdDecVarUser() declares the user signal variable to VCD file writer.
  • startVcdDecVarUser() responses to bind signal from generated file to main simulator

callback methods

  • checkCallBack() will check the call back constrain from user. if the constraint met the model will kick back to main simulation process (kathryn)
simulationGeneration