Simulation Interface

Simulation interface is the stating point for designers to write testbench and manage their simulation

•   class mySim :public SimAutoInterface{
      MyModule* _md;
      void describe(){
        incCycle(13);
        sim { /// cyclc 13
          if ((ull)(*_md->ack) == 1){
              sim{incCycle((ull)_md->fVal);
              anotherMethod1();
              };
          }
          if ((ull)(*_md->ab) == 1){
              sim{incCycle((ull)_md->gVal);
              anotherMethod2();};
          }
        };
      }
      void describeCon(){
        for(int i = 0; i < 17; i++){
         testAndPrint("test", ull(_md->result), 0);
         conNextCycle(1);
        }
      }
      void describeModelTrigger(){ 
          trig(_md.res == 1, [&](){cbFunc();});
      }
    };

• To simulate in HS, designers may build their own class and inherit SimAutoInterface base class, so there are 3 major class methods/features that designers can describe their behavior.(optional)

  • void describe ():

    • we use sim block to declare simulation events.
    • the code inside "sim" block will be invoked when the simulator meet the specified cycle.
    • designers can specify cycle number using incCycle(#number);
    • the simulation block have sub simulation block to compute other event.

  • void describeCon ():

    • it is used to be a independent run aside thread that executes synchronously with simulation controller,
    • the conNextCycle(2) is used to specify cycle when it should be executed.
    • it resembles testbench in Verilog

  • describeModelTrigger():

    • the hardware model is capalbe for run multiple cycle at time to performance optimization.
    • Therefore, the callback condition is use to probe the model when the model meet the condition the model will call the specified function.
    • use trig(#condtion, #callbackfunction(void ()));