Hardware Components
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In Kathryn, hardware components refers to both physical and logical elements of the hardware design model and they are internally composed of 6 major types.
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Type description Reg storable hardware component, only sensitive to posedge clk src: src/model/hwComponent/register/register.hWire non-storable hardware component, sensitive to all signal propagation src: src/model/hwComponent/wire/wire.hValue constant value src: src/model/hwComponent/value/value.hNest concatenate hardware components in single variable src: src/model/hwComponent/expression/nest.hMemBlock array storable hardware component, only sensitive to posedge clk src: src/model/hwComponent/memBlock/MemBlock.hMemBlockAgent the indexer of the Memblock, storation sensitive to posedge clk, retrieve sensitive to all signal src: src/model/hwComponent/memBlock/MemBlockAgent.hexpression represent the combitional logic src: src/model/hwComponent/expression/expression.hSliceAgent slice hardware component src: src/model/hwComponent/abstract/slicable.h
Hardware Component Structure
- This section illustrates how hardware components are structured.
AssignOpr<H>manages interface for designers to assign the value to its element.Assignablemanages the signal behavior for its element.Operableprovides interface for signal operation such as bitwise, arithmethic, etc.Slicable<H>manages bit slicing for each element.AssignCallbackFromAgent<H>provides interface for interacting withSlicable<H>Identifiablemanages names, component id, localization for its component.HwCompControllerItfprovides communication between its component and model controllerModelDebuggableprovides interface for debuggable.LogicSimEngineInterfaceprovides interface for letting simulation engine to retrive model meta-dataLogicGenInterfaceprovides interface for letting Verilog Generation engine to retrieve model meta-dataMemSimEngineInterfaceprovides interface MemBlk for letting simulation engine to rertrive model meta-data