Motivation

When I was in my second year as an undergraduate computer engineering student, I tried to build an out-of-order superscalar CPU with the RISC-V instruction set. I found that writing Verilog and SystemVerilog led me to feel frustrated because thinking about logic in parallel is sometimes difficult. Moreover, When I joined the FPGA design camp in 2023, I found that my fellows were still upset in writing Hardware Simulations so they got stuck in their design because they didn't know where it was going wrong. I think that it would be better if there was a framework or tool that could facilitate Hardware design, especially in hardware control flow.

As a matter of fact, Chisel (A Modern Hardware Design Language) has inspired me to see how powerful the programming language can enhance the hardware design progress. So, I think that we can achieve better Design Space Exploration (DSE) via higher abstraction of hardware control flow, a unified simulator with a zero-effort profiling tool, etc.

Therefore, This project introduces KATHRYN a hybrid approach for Hardware modeling, simulation, and synthesis to offer the new hardware design method embedded in C++ programming language (bind with Python in the future) to address the crux that I suffered in the past.